Self-Checking Conditional-Sum Adder Design Based on Two-Rail Encoding Scheme

In this paper, we propose the self-checking conditional-sum adder design based on two-rail encoding scheme. The proposed high reliability adder structure is modulized and mainly composed of 2-bit self-checking conditional-sum adder modules. Both the carry-bits and sum-bits of the adder are encoded based on two-rail encoding scheme, and the encoding carry-bits and sum-bits are checked by the self-testing two-pair two-rail checkers. Multiplexers used in the adder design also conform to have the totally self-checking capability. The proposed design can make a conditional-sum adder carry out the totally-self-checking capability during processing arithmetic operations, and thus improve the reliability of the adder. A real silicon self-checking conditional-sum adder is implemented based on the TSMC 0.35um 2p4m mixed mode process technology. The experiment has proved the proposed self-checking conditional-sum adder is valid and practical.

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