Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs - Concepts, constraints and solutions

Abstract Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.

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