Optimization of back pressure and throughput for latency insensitive systems

Latency insensitive protocols (LIP) were originally based on valid/stall handshakes between components and relays stations. However, for designs whose connection graph is a single strongly connected component(SCC), it was shown that static scheduling of computation achieves better throughput. Unfortunately, for a system composed of multiple SCCs such global static scheduling is not possible. Recent work has shown how to minimize back pressure (stall) based flow control for such systems. However, that solution does not necessarily achieve optimal throughput because it only minimizes back-pressure without attempting to optimize throughput. Throughput optimizing solutions for latency insensitive systems also exists, which require a mixed Integer Linear Programming (MILP) solution that inevitably does not scale for large systems. Moreover, that throughput optimizing solution uses back pressure for every connection leading to area overhead and further interconnect routing issues. In this paper, we consider an optimization technique for the synthesis of latency insensitive systems. In particular, we consider a synchronous hardware system which is composed of multiple SCCs. We provide algorithm for synthesizing a latency insensitive implementation which minimizes back-pressure while maximizing throughput. Our approach scales because we formulate MILP whose size is significantly smaller than that of the previous throughput optimizing MILP formulation. To the best of our knowledge, this is the first optimization technique considering both back pressure and throughput of latency insensitive system in the literature.

[1]  Donald B. Johnson,et al.  Efficient Algorithms for Shortest Paths in Sparse Networks , 1977, J. ACM.

[2]  Robert E. Tarjan,et al.  Depth-First Search and Linear Graph Algorithms , 1972, SIAM J. Comput..

[3]  Julien Boucaron,et al.  Formal Methods for Scheduling of Latency-Insensitive Designs , 2007, EURASIP J. Embed. Syst..

[4]  Jordi Cortadella,et al.  Performance optimization of elastic systems using buffer resizing and buffer insertion , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Cheng-Kok Koh,et al.  Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels , 2003, ICCAD 2003.

[6]  Jordi Cortadella,et al.  Synthesis of synchronous elastic architectures , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Pradip Bose,et al.  Synchronous interlocked pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[8]  Robert E. Tarjan,et al.  Finding optimum branchings , 1977, Networks.

[9]  Sandeep K. Shukla,et al.  Minimizing back pressure for latency insensitive system synthesis , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[10]  Karsten Wolf,et al.  LoLA: A Low Level Analyser , 2000, ICATPN.

[11]  Sandeep K. Shukla,et al.  Analysis of scheduled Latency insensitive systems with periodic clock calculus , 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

[12]  Mario R. Casu,et al.  A new approach to latency insensitive design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[13]  Luca P. Carloni The Role of Back-Pressure in Implementing Latency-Insensitive Systems , 2006, Electron. Notes Theor. Comput. Sci..

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.