A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier

A 10 Gbase-LX4 receiver front end including an inductor feedback transimpedance amplifier and a modified Cherry-Hooper cell limiting amplifier realized in a 0.18 /spl mu/m CMOS process is described. The receiver front end covers 34.8 dB input dynamic range and provides 66 dB/spl Omega/ differential gain with 1.7 GHz bandwidth. All the building blocks achieve a high data rate with low power dissipation. The receiver front end can meet the BER requirement under all corner simulations with 113 ps(pp) data jitter at 3.125 Gb/s. The chip area is 1.1/spl times/2.2 mm/sup 2/ and consumes 54 mW using 1.8 V supply voltage. The overall performance is verified by the measured results.

[1]  Ryoji Takeyari,et al.  A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links , 1997 .

[2]  H. Kim,et al.  A 12 GHz 30 dB modular BiCMOS limiting amplifier for 10 Gb SONET receiver , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  Kuo-Chiang Hsieh,et al.  A 10 Gb/s Si-bipolar TX/RX chipset for computer data transmission , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[4]  S. L. Sundaram,et al.  Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links , 1995 .

[5]  S. Chandrasekhar,et al.  A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver , 2001 .

[6]  Behzad Razavi.  Design of intergrated circuits for optical communications , 2002 .