A LOW POWER CMOS ELECTROCARDIOGRAM AMPLIFIER DESIGN USING 0.18µM CMOS TECHNOLOGY

An electrocardiogram (ECG) amplifier was designed in 0.18 µm standard CMOS technology with the power consumption of 1.47µw, 54.5�݌√ܪݖ ⁄ input-referred noise, and a common-mode rejection ratio of 82 dB. The ECG amplifier was designed that pick-up the lower power signal from the heart. The main challenge includes amplifying the weak signal in the presence of noise. The OTA design is well utilized to remove the flicker noise. The performance of the ECG amplifier can be improved by input transistor sizing, device matching and gain-setting adaptive element. Compared to previous work [1], the signal quality is better with less power consumption. The amplified signal can be processed and send to the hospital via wireless transceiver.

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