Calibration of Abstract Performance Models for System-Level Design Space Exploration
暂无分享,去创建一个
Andy D. Pimentel | Mark Thompson | Simon Polstra | Cagkan Erbas | M. Thompson | Simon Polstra | A. Pimentel | C. Erbas | Cagkan Erbas
[1] Todor Stefanov,et al. pn: A Tool for Improved Derivation of Process Networks , 2007, EURASIP J. Embed. Syst..
[2] Andy D. Pimentel,et al. An IDF-based trace transformation method for communication refinement , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[3] Ed F. Deprettere,et al. Laura: Leiden Architecture Research and Exploration Tool , 2003, FPL.
[4] Jean Paul Calvez,et al. Uninterpreted co-simulation for performance evaluation of Hw/Sw systems , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.
[5] Luciano Lavagno,et al. Hardware-Software Co-Design of Embedded Systems , 1997 .
[6] Andy D. Pimentel,et al. A software framework for efficient system-level performance evaluation of embedded systems , 2003, SAC '03.
[7] Andrew S. Cassidy,et al. Layered, multi-threaded, high-level performance design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[8] Paolo Giusto,et al. Reliable estimation of execution time of embedded software , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[9] Luciano Lavagno,et al. Hardware-software co-design of embedded systems: the POLIS approach , 1997 .
[10] Amer Baghdadi,et al. Design space exploration for hardware/software codesign of multiprocessor systems , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[11] Richard M. Fujimoto,et al. Parallel discrete event simulation , 1990, CACM.
[12] Rainer Leupers,et al. Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs , 2008, SAMOS.
[13] Edward A. Lee,et al. Dataflow process networks , 1995, Proc. IEEE.
[14] Alexandru Turjan,et al. System design using Khan process networks: the Compaan/Laura approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[15] Andy D. Pimentel,et al. On the Calibration of Abstract Performance Models for System-level Design Space Exploration , 2006, ICSAMOS.
[16] Erwin A. de Kock,et al. COSY communication IP's , 2000, Proceedings 37th Design Automation Conference.
[17] Ed F. Deprettere,et al. An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures , 1997, ASAP.
[18] Matthias Gries,et al. Methods for evaluating and covering the design space during early design development , 2004, Integr..
[19] Andy D. Pimentel,et al. A systematic approach to exploring embedded system architectures at multiple abstraction levels , 2006, IEEE Transactions on Computers.
[20] Todor Stefanov,et al. Improved derivation of process networks , 2006 .
[21] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[22] Mayan Moudgill,et al. Environment for PowerPC microarchitecture exploration , 1999, IEEE Micro.
[23] Viktor K. Prasanna,et al. Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[24] Soonhoi Ha,et al. Trace-driven HW/SW cosimulation using virtual synchronization technique , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[25] Luciano Lavagno,et al. Metropolis: An Integrated Electronic System Design Environment , 2003, Computer.
[26] Andy D. Pimentel,et al. A Mixed-level Co-simulation Method for System-level Design Space Exploration , 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.
[27] Timo Hämäläinen,et al. UML-based multiprocessor SoC design framework , 2006, TECS.
[28] Gilles Kahn,et al. The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.
[29] Luca Benini,et al. SystemC Cosimulation and Emulation of Multiprocessor SoC Designs , 2003, Computer.
[30] John Paul Shen,et al. Calibration of Microprocessor Performance Models , 1998, Computer.
[31] Alexandru Turjan,et al. Translating affine nested-loop programs to process networks , 2004, CASES '04.
[32] D PimentelAndy,et al. A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels , 2006 .
[33] K. Keutzer,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[34] Stamatis Vassiliadis,et al. The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.
[35] Todd M. Austin,et al. SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.
[36] Viktor K. Prasanna,et al. A hierarchical simulation framework for application development on system-on-chip architectures , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[37] Ed F. Deprettere,et al. Multi-processor system design with ESPAM , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[38] Ahmed Amine Jerraya,et al. Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures , 2001, ASP-DAC '01.
[39] Ed F. Deprettere,et al. Algorithmic transformation techniques for efficient exploration of alternative application instances , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).