A Hardware Implementation Method of Multi-Objective Genetic Algorithms

Multi-objective genetic algorithms (MOGAs) are approximation techniques to solve multi-objective optimization problems. Since MOGAs search a wide variety of pareto optimal solutions at the same time, MOGAs require large computation power. In order to solve practical sizes of the multi objective optimization problems, it is desirable to design and develop a hardware implementation method for MOGAs with high search efficiency and calculation speed. In this paper, we propose a new method to easily implement MOGAs as high performance hardware circuits. In the proposed method, we adopt simple Minimal Generation Gap (MGG) model as the generation model, because it is easy to be pipelined. In order to preserve diversity of individuals, we need a special selection mechanism such as the niching method which takes large computation time to repeatedly compare superiority among all individuals in the population. In the proposed method, we developed a new selection mechanism which greatly reduces the number of comparisons among individuals, keeping diversity of individuals. Our method also includes a parallel execution architecture based on Island GA which is scalable to the number of concurrent pipelines and effective to keep diversity of individuals. We applied our method to multi-objective Knapsack Problem. As a result, we confirmed that our method has higher search efficiency than existing method.

[1]  Kalyanmoy Deb,et al.  A Fast Elitist Non-dominated Sorting Genetic Algorithm for Multi-objective Optimisation: NSGA-II , 2000, PPSN.

[2]  Prabhas Chongstitvatana,et al.  A hardware implementation of the Compact Genetic Algorithm , 2001, Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546).

[3]  Teruo Higashino,et al.  A flexible and high-reliable HW/SW codesign method for real-time embedded systems , 2004, 25th IEEE International Real-Time Systems Symposium.

[4]  Sadiq M. Sait,et al.  Iterative computer algorithms with applications in engineering - solving combinatorial optimization problems , 2000 .

[5]  Hiroto Yasuura,et al.  High-performance hardware design and implementation of genetic algorithms , 2001 .

[6]  Erick Cantú-Paz,et al.  A Survey of Parallel Genetic Algorithms , 2000 .

[7]  Hisashi Shimodaira.  An Empiricañ Performance Comparison of Niching Methods for Genetic Algorithms , 2002 .

[8]  Shin'ichi Wakabayashi,et al.  Genetic algorithm accelerator GAA-II , 2000, ASP-DAC '00.

[9]  Bernd Scheuermann,et al.  Population based ant colony optimization on FPGA , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[10]  Keiichi Yasumoto,et al.  General Architecture for Hardware Implementation of Genetic Algorithm , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[11]  Hiroaki Satoh,et al.  Minimal generation gap model for GAs considering both exploration and exploitation , 1996 .

[12]  André DeHon,et al.  Hardware-assisted simulated annealing with application for fast FPGA placement , 2003, FPGA '03.

[13]  Hideki Ando,et al.  A custom computing machine for genetic algorithms without pipeline stalls , 1999, IEEE SMC'99 Conference Proceedings. 1999 IEEE International Conference on Systems, Man, and Cybernetics (Cat. No.99CH37028).

[14]  Marco Laumanns,et al.  SPEA2: Improving the strength pareto evolutionary algorithm , 2001 .