Formally Modeling Microprocessor Caches and Branch Predictors

Microprocessors are subject to many hard constraints related to performance, power consumption, worst-case execution time, reliability, dependability, etc. Prooving any of these properties is currently nearly impossible. We believe that such proofs could be made if formal models of microprocessors were available. For these reasons, we formally model the operation of caches and branch predictors. These are structures that are present in virtually all microprocessors and have a high impact on the above mentioned system properties. Key-words: operational semantics, microarchitecture, cache

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