Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
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Amer Baghdadi | Guido Masera | Michel Jézéquel | Fabrizio Vacca | Hazem Moussa | A. Baghdadi | M. Jézéquel | G. Masera | F. Vacca | H. Moussa
[1] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[2] David J. C. MacKay,et al. Good Error-Correcting Codes Based on Very Sparse Matrices , 1997, IEEE Trans. Inf. Theory.
[3] D. Houzet,et al. A complete 4G radiocommunication application mapping onto a 2D mesh NoC architecture , 2006, 2006 IEEE North-East Workshop on Circuits and Systems.
[4] Shyh-Jye Jou,et al. An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications , 2008, IEEE Journal of Solid-State Circuits.
[5] Bella Bose,et al. Fault-Tolerant Ring Embedding in de Bruijn Networks , 1993, IEEE Trans. Computers.
[6] Guido Masera,et al. Interconnection framework for high-throughput, flexible LDPC decoders , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[7] Guido Masera,et al. Finite precision implementation of LDPC decoders , 2005 .
[8] Guido Masera,et al. Implementation of a Flexible LDPC Decoder , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[9] X. Jin. Factor graphs and the Sum-Product Algorithm , 2002 .
[10] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[11] de Ng Dick Bruijn. A combinatorial problem , 1946 .
[12] Ajay Dholakia,et al. Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.
[13] Frank Kienle,et al. Low Complexity LDPC Code Decoders for Next Generation Standards , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[14] Dhiraj K. Pradhan,et al. The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI , 1989, IEEE Trans. Computers.
[15] Sergio Benedetto,et al. Mapping interleaving laws to parallel turbo and LDPC decoder architectures , 2004, IEEE Transactions on Information Theory.
[16] Wei-Feng Fang,et al. A binary tree architecture for application specific network on chip (ASNOC) design , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..
[17] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[18] Dhiraj K. Pradhan,et al. Reliable network-on-chip based on generalized de Bruijn graph , 2007, 2007 IEEE International High Level Design Validation and Test Workshop.
[19] George Karypis,et al. Introduction to Parallel Computing , 1994 .
[20] Amer Baghdadi,et al. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[21] Luca Benini. Application Specific NoC Design , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[22] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[23] Axel Jantsch,et al. Network on Chip : An architecture for billion transistor era , 2000 .
[24] Brendan J. Frey,et al. Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.
[25] E. Boutillon,et al. Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study , 2008, 2008 IEEE 10th International Symposium on Spread Spectrum Techniques and Applications.
[26] Giovanni De Micheli,et al. Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.
[27] DaeHo Seo,et al. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks , 2005, ISCA 2005.
[28] Narayanan Vijaykrishnan,et al. Implementing LDPC decoding on network-on-chip , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[29] Xin-Yu Shih,et al. An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$m CMOS Process , 2008, IEEE Journal of Solid-State Circuits.