论文信息 - Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture

Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture

A low-power, high speed direct digital frequency synthesizer (DDFS) is presented. Some approximations are used to avoid using a large ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the compressed ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a DDFS has been implemented using Taylor's series. The spurious-free dynamic range is about 40 decibels at low synthesized frequencies.

M. Rehan | M.N. Khan | M.S. Imran | U. Hai

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