A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.

[1]  B. Nauta,et al.  A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects , 2006, IEEE Journal of Solid-State Circuits.

[2]  Giovanni De Micheli,et al.  Power and Reliability Management of SoCs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Maryam Shojaei Baghini,et al.  A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects , 2009, GLSVLSI '09.

[4]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  William J. Dally,et al.  Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.

[6]  David Blaauw,et al.  High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[7]  Wayne P. Burleson,et al.  An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[8]  Wayne P. Burleson,et al.  Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  David Blaauw,et al.  Self-Timed Regenerators for High-Speed and Low-Power Interconnect , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[10]  Justin Schauer,et al.  High Speed and Low Energy Capacitively Driven On-Chip Wires , 2008, IEEE Journal of Solid-State Circuits.

[11]  N. Tzartzanis,et al.  Differential current-mode sensing for efficient on-chip global signaling , 2005, IEEE Journal of Solid-State Circuits.

[12]  S. Wong,et al.  Near speed-of-light signaling over on-chip electrical interconnects , 2003 .

[13]  N. Masoumi,et al.  High speed current-mode signalling for interconnects considering transmission line and crosstalk effects , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[14]  Harry J. M. Veendrick,et al.  High speed current-mode signaling circuits for on-chip interconnects , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[15]  Himanshu Kaul,et al.  Low-power on-chip communication based on transition-aware global signaling (TAGS) , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Ramalingam Sridhar,et al.  A low-power asymmetric source driver level converter based current-mode signaling scheme for global interconnects , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[17]  Maryam Shojaei Baghini,et al.  Energy efficient current-mode signaling scheme , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[18]  Eisse Mensink,et al.  Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects , 2010, IEEE Journal of Solid-State Circuits.

[19]  M. Horowitz,et al.  Efficient on-chip global interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[20]  Jian Xu,et al.  A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling , 2006, IEEE Custom Integrated Circuits Conference 2006.