FPGA-based hardware realization for 4G MIMO wireless systems

Emerging multiple-input multiple-output (MIMO) systems are called to play a key role in fourth generation (4G) wireless systems in order to achieve higher data rate and advanced spectral efficiency. Even with extensive research on the design of transmission and reception algorithms, little is known about the complexity of hardware implementation. The MIMO encoder design and implementation is straight forward, however, the decoder implementation is little more complex as it requires resource utilization. This paper presents an efficient hardware realization of MIMO systems that utilizes the resources of the device by adopting the technique of parallelism. The hardware is designed and implemented on a Xilinx Virtex™-4 XC4VLX60 Field Programmable Gate Arrays (FPGA) device. In this paper, a comprehensive explanation of the complete design process is provided, including an illustra- tion of the tools used in its development. The results are obtained for 2×2 MIMO system for coding and decoding at the transmitter and the receiver. The system is developed based on modular design which simplifies system design, eases hardware update and facilitates testing the various modules in an independent manner.

[1]  Lutz H.-J. Lampe,et al.  Multiple-antenna techniques for wireless communications - a comprehensive literature survey , 2009, IEEE Communications Surveys & Tutorials.

[2]  Yong Soo Cho,et al.  An FPGA Implementation of MML-DFE for Spatially Multiplexed MIMO Systems , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  André Bourdoux,et al.  Implementation Aspects and Testbeds for MIMO Systems , 2006, EURASIP J. Adv. Signal Process..

[4]  Mohammad Tariqul Islam,et al.  Performance and complexity improvement of training based channel estimation in MIMO systems , 2009 .

[5]  Siavash M. Alamouti,et al.  A simple transmit diversity technique for wireless communications , 1998, IEEE J. Sel. Areas Commun..

[6]  Erik G. Larsson,et al.  Space-Time Block Coding for Wireless Communications , 2003 .

[7]  Ahmed M. Eltawil,et al.  Design and Implementation of a Scalable Channel Emulator for Wideband MIMO Systems , 2009, IEEE Transactions on Vehicular Technology.

[8]  Ian Vince McLoughlin,et al.  An FPGA-Based MIMO and Space-Time Processing Platform , 2006, EURASIP J. Adv. Signal Process..

[9]  Babak Daneshrad,et al.  Multi-antenna testbeds for research and education in wireless communications , 2004, IEEE Communications Magazine.

[10]  Y. Nagao,et al.  Design of 600Mbps 4×2 MIMO-OFDM Wireless LAN System and Its FPGA Implementation , 2008, 2008 10th International Conference on Advanced Communication Technology.

[11]  Carl Ebeling,et al.  Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture , 2004, IEEE Trans. Computers.

[12]  Helmut Bölcskei,et al.  An overview of MIMO communications - a key to gigabit wireless , 2004, Proceedings of the IEEE.

[13]  Robert Langwieser,et al.  Vienna MIMO Testbed , 2006, EURASIP J. Adv. Signal Process..

[14]  Angel Fernandez Herrero,et al.  Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver , 2008, VLSI Design.

[15]  Gang Li,et al.  Beyond 3G Evolution , 2008, IEEE Vehicular Technology Magazine.

[16]  I.V. McLoughlin,et al.  FPGA implementation of space-time block coding systems , 2004, Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication (IEEE Cat. No.04EX710).