VLSI Architecture of a High Performance FFT Processor
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The VLSI architecture of a high performance FFT processor is described in the paper A particularly simple way to control radix4 FFT hardware is developed The method produces the indices both for inputs of each butterfly operation and for the appropriate twiddle factors The memory assignment is "inplace" to minimize memory size,and memorybank conflictfree to allow simultaneous access to the four data needed for calculation of each of the radix4 butterflies,hence the processor can access all the operands concurrently in one cycle Using Verilog HDL,a 1024point FFT processor is designed,which can process frames of 16bit complex samples at one output sample per 100 MHz clock cycle,thus performing a 1024point transform in 128 μs