Techniques for Cache and Memory Simulation Using Address Reference Traces

Simulation using address reference traces is one of the primary methods for the performance evaluation of the memory hierarchy of computer systems. In this paper we survey the techniques used in such a simulation. In both the uniprocessor and shared-memory multiprocessor cases, the issues can be divided into trace collection, trace storage, and trace usage. Trace collection can employ several hardware or software methods. Common concerns are that the collection method capture all of the address references of interest, that the execution overhead of the collection method is not excessive, and that the trace is of adequate length. The increasing size of caches heightens the adequate length concern. Trace storage is of concern because of the large size of traces. Techniques for trace compression and trace reduction have been developed. Trace usage is of concern because of the length of a simulation. Under some circumstances it is possible to evaluate multiple cache sizes in a single pass of the trace. For multiprocessor traces it is also possible to simulate the trace in parallel to achieve speedup. In the multiprocessor case, the global trace problem arises because environment-dependent address changes prevent the adjustment of traces collected in one environment from re ecting a di erent environment. A relatively new technique, inline simulation, attempts to avoid a number of the problems associated with traditional trace-driven simulation. Index Terms address reference traces, trace-driven simulation, survey, inclusion property, trace reduction, one-pass simulation, parallel traces, global trace problem, inline simulation. 2

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