论文信息 - Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughput and lower power dissipation than the Intel 80C51. The new architecture focuses on combining increased performance with low power dissipation.<<ETX>>

L. G. Clonts | Donald W. Bouldin

[1] L. G. Clonts,et al. Writing area-efficient hardware descriptions for logic synthesis , 1992, Proceedings IEEE Southeastcon '92.

[2] David Harrison,et al. Data management and graphics editing in the berkeley design environment , 1986 .

[3] Milos D. Ercegovac,et al. A novel CMOS implementation of double-edge-triggered flip-flops , 1990 .

[4] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.