DIGITAL DOWN CONVERTER IMPLEMENTATION OF ASIC USING IN IP

Multirate systems are the systems that function at multiple sample periods. One example of such a system is a Digital Down Converter, used in digital communication receivers. Digital down conversion is a basic process of any digital communication receiver, where the bandwidth of the beloved channel centered at carrier frequency, is shifted down to baseband signal centered at zero frequency. Any digital communication receiver will have an Analog to Digital Converter, sampling and digitizing the selected channel at tens or hundreds of MHz, thus producing a very high data rate. It is outside the real time computational capabilities of the slower software processors to further process this signal at such a high rate. The DDC is placed in between the fast ADC and the slower signal processors, in a digital communication receiver. The DDC basically performs two functions. It first downconverts the bandwidth of the selected channel to baseband i.e. centered at zero frequency, and then it reduces the sample rate or downsamples the signal to a lower rate. By doing so, it becomes easier for the following stages, which consists of lower speed processors to further process the signal. DDC’s are most usually implemented in logic using Field Programmable Gate Arrays or Application Specific Integrated Circuits. In the course of this project, one such DDC is implemented in ASIC, which can be later used as an Intellectual Property.