Pi-Gate SOI MOSFET

This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET.

[1]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[2]  Jean-Pierre Colinge,et al.  Silicon-on-insulator 'gate-all-around' MOS device , 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

[3]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[4]  J. Denton,et al.  Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate , 1996, IEEE Electron Device Letters.

[5]  X. Baie,et al.  A silicon-on-insulator quantum wire , 1996 .

[6]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[7]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[8]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .