A new class of easily testable assignment decision diagrams

This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a testability property called thru function. The thru-testable ADDs is an easily-testable set of thru functions that allows data transfer from its input to its output. We also define a design-for-testability (DFT) method to augment a given ADD with thru functions so that the ADD becomes thru-testable. We compare the circuits modified using our proposed method with the original circuits and partial scan designed circuits in terms of fault efficiency, area overhead, test generation time and test application time. Since the proposed DFT method is introduced at a high level, which deals with less number of gates, the information of thru functions can be extracted more easily. As a result, it lowers the area overhead compared to partial scan.

[1]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[2]  Viraphol Chaiyakul,et al.  High-Level Transformations for Minimizing Syntactic Variances , 1993, 30th ACM/IEEE Design Automation Conference.

[3]  Niraj K. Jha,et al.  A BIST scheme for RTL controller-data paths based on symbolic testability analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[4]  Christos A. Papachristou,et al.  A built-in self-testing approach for minimizing hardware overhead , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  Toshimitsu Masuzawa,et al.  A non-scan DFT method at register-transfer level to achieve complete fault efficiency , 2000, Proceedings - Design Automation Conference.

[6]  Janak H. Patel,et al.  High-level variable selection for partial-scan implementation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[7]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[8]  Hideo Fujiwara,et al.  A DFT Method for Time Expansion Model at Register Transfer Level , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[9]  Toshimitsu Masuzawa,et al.  Design for strong testability of RTL data paths to provide complete fault efficiency , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[10]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[11]  Christos A. Papachristou,et al.  Testability analysis and insertion for RTL circuits based on pseudorandom BIST , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[12]  Toshimitsu Masuzawa,et al.  A non-scan DFT method for controllers to achieve complete fault efficiency , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[13]  Daniel D. Gajski,et al.  Assignment Decision Diagram for High-Level Synthesis , 1992 .

[14]  Nilanjan Mukherjee,et al.  On RTL scan design , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[15]  Hideo Fujiwara A New Class of Sequential Circuits with Combinational Test Generation Complexity , 2000, IEEE Trans. Computers.

[16]  Hideo Fujiwara,et al.  Logic Testing and Design for Testability , 1985 .

[17]  Chia Yee Ooi,et al.  A New Class of Sequential Circuits with Acyclic Test Generation Complexity , 2006, 2006 International Conference on Computer Design.

[18]  Masahiro Fujita,et al.  Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[20]  Miodrag Potkonjak,et al.  Non-scan Design-for-testability Of Rt-level Data Paths , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[21]  Sujit Dey,et al.  H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads , 1996, Proceedings of 14th VLSI Test Symposium.