An Automatic Test Generation Algorithm for Hardware Description Languages

A new approach to test generation from Hardware Description Language circuit models has been developed and implemented. The described E-algorithm generates tests for control, operation, and data faults in sequential and combinational logic modeled at the functional level. A symbolic variable notation is introduced to permit systematic fault propagation through control structures. Results of the implementation are given for a set of test cases and the application of the algorithm to a semi-custom ASIC are discussed.

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