Interconnect Energy Dissipation in

This paper presents a detailed empirical study and an- alytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing. This is in sharp con- trast with the steady-state analysis, which states that driver size has no impact on the energy dissipation per output change. In ad- dition, we propose a new design metric which is the product of en- ergy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay, and the percentage of maximum undershoot when the circuit exhibits an underdamped behavior. This metric is used during the driver sizing problem for- mulation for minimum energy-delay-ringing product. The experi- mental results carried out by HSPICE simulation verify the accu- racy of our models.

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