Clock Signal in Electronic Systems

This chapter contains sections titled: The Significance of Clock Signal The Characteristics of Clock Signal Clock Signal Driving Digital System Clock Signal Driving Sampling System Extracting Clock Signal From Data: Clock Data Recovery Clock Usage in System-on-Chip Two Fields: Clock Generation and Clock Distribution Bibliography ]]>

[1]  Y. Akazawa,et al.  Jitter analysis of high-speed sampling systems , 1990 .

[2]  Ramesh Harjani,et al.  Design of low-phase-noise CMOS ring oscillators , 2002 .

[3]  B. Razavi,et al.  Challenges in the design of high-speed clock and data recovery circuits , 2002, IEEE Commun. Mag..

[4]  Andrea Neviani,et al.  Analysis of the impact of process variations on clock skew , 2000 .

[5]  T.H. Lee,et al.  Oscillator phase noise: a tutorial , 1999, IEEE Journal of Solid-State Circuits.

[6]  A. Demir Phase noise and timing jitter in oscillators with colored-noise sources , 2002 .

[7]  Andreas Wiesbauer,et al.  On the jitter requirements of the sampling clock for analog-to-digital converters , 2002 .

[8]  Masashi Shimanouchi,et al.  An approach to consistent jitter modeling for various jitter aspects and measurement methods , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[9]  Andrzej Cichocki,et al.  Fundamentals of Sampled-Data Systems , 1989 .

[10]  Leopoldo Angrisani,et al.  Modeling timing jitter effects in digital-to-analog converters , 2005, IEEE International Workshop on Intelligent Signal Processing, 2005..

[11]  Alper Demir,et al.  Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  C. Sandner,et al.  Numerical modeling of PLL jitter and the impact of its non-white spectrum on the SNR of sampled signals , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

[13]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[14]  Antonio Cantoni,et al.  Phase jitter≡timing jitter? , 1998, IEEE Commun. Lett..

[15]  Parameswaran Ramanathan,et al.  Clock distribution in general VLSI circuits , 1994 .

[16]  K. S. Kundert Introduction to RF simulation and its application , 1999 .

[17]  Eby G. Friedman,et al.  Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.

[18]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[19]  Arthur H. M. van Roermund,et al.  A general analysis on the timing jitter in D/A converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[20]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.

[21]  H. Tao,et al.  Analysis of timing jitter in bandpass sigma-delta modulators , 1999 .

[22]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[23]  Yih-Chyun Jenq Direct digital synthesizer with jittered clock , 1997 .

[24]  Ramesh Harjani,et al.  Comparison and analysis of phase noise in ring oscillators , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[25]  R. Dutton,et al.  Minimum achievable phase noise of RC oscillators , 2005, IEEE Journal of Solid-State Circuits.

[26]  Liming Xiu The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture , 2008, IEEE Circuits and Systems Magazine.

[27]  Young-wan Kim,et al.  Phase Noise Model of Single Loop Frequency Synthesizer , 2008, IEEE Transactions on Broadcasting.

[28]  Mark Horowitz,et al.  High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.

[29]  Mark Horowitz,et al.  Timing analysis including clock skew , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Liming Xiu Some open issues associated with the new type of component: digital-to-frequency converter [Open Column] , 2008, IEEE Circuits and Systems Magazine.

[31]  T. M. Mak Jitters in high performance microprocessors , 2008, 2008 IEEE International Test Conference.

[32]  Mani Soma,et al.  A Time Domain Method to Measure Oscillator Phase Noise , 2009, 2009 27th IEEE VLSI Test Symposium.

[33]  Xiaohong Jiang,et al.  Statistical skew modeling for general clock distribution networks in presence of process variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..