Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm
暂无分享,去创建一个
Sofiène Tahar | Nawwaf N. Kharma | Ali Habibi | Amer Samarah | N. Kharma | A. Habibi | S. Tahar | Amer Samarah
[1] Wolfgang Roesner,et al. Comprehensive Functional Verification: The Complete Industry Cycle , 2005 .
[2] Elizabeth M. Rudnick,et al. Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation , 1995, 32nd Design Automation Conference.
[3] S. Tahar,et al. Assertion based verification of PSL for SystemC designs , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[4] Kurt Keutzer,et al. Coverage Metrics for Functional Validation of Hardware Designs , 2001, IEEE Des. Test Comput..
[5] Pierre Faye,et al. Improved Design Verification by Random Simulation Guided by Genetic Algorithms , 2001 .
[6] Sofiène Tahar,et al. Towards a faster simulation of SystemC designs , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).
[7] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[8] Irith Pomeranz,et al. On improving genetic optimization based test generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.
[9] Zbigniew Michalewicz,et al. Genetic Algorithms + Data Structures = Evolution Programs , 1996, Springer Berlin Heidelberg.
[10] Takuji Nishimura,et al. Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator , 1998, TOMC.
[11] Giovanni Squillero,et al. Automatic test program generation: a case study , 2004, IEEE Design & Test of Computers.
[12] Jongshin Shin,et al. A genetic approach to automatic bias generation for biased random instruction generation , 2001, Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546).
[13] Avi Ziv. Cross-product functional coverage measurement with temporal properties-based assertions [logic verification] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[14] Ilan Beer,et al. FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.
[15] Janick Bergeron,et al. Writing Testbenches: Functional Verification of HDL Models , 2000 .
[16] Surrendra Dudani,et al. High level functional verification closure , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[17] Sarfraz Khurshid,et al. Exploring very large state spaces using genetic algorithms , 2004, International Journal on Software Tools for Technology Transfer.
[18] Laurent Fournier,et al. Functional verification methodology for microprocessors using the Genesys test-program generator , 1999, DATE '99.
[19] Sofiène Tahar,et al. Design and verification of SystemC transaction-level models , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[20] Bob Bentley. High level validation of next-generation microprocessors , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..
[21] Nicholas J. Radcliffe,et al. The algebra of genetic algorithms , 1994, Annals of Mathematics and Artificial Intelligence.
[22] Zbigniew Michalewicz,et al. Genetic Algorithms + Data Structures = Evolution Programs , 1992, Artificial Intelligence.
[23] Jack Donovan,et al. SystemC: From the Ground Up , 2004 .
[24] Thomas Kropf,et al. Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.
[25] Laurent Fournier,et al. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[26] Bryan F. Jones,et al. Automatic structural testing using genetic algorithms , 1996, Softw. Eng. J..
[27] Avi Ziv,et al. Coverage directed test generation for functional verification using Bayesian networks , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[28] M.H. Hassoun,et al. Fundamentals of Artificial Neural Networks , 1996, Proceedings of the IEEE.
[29] Shmuel Ur,et al. Micro architecture coverage directed generation of test programs , 1999, DAC '99.
[30] Avi Ziv,et al. Hole analysis for functional coverage data , 2002, DAC '02.
[31] Donald E. Knuth,et al. The art of computer programming. Vol.2: Seminumerical algorithms , 1981 .
[32] Allon Adir,et al. Genesys-Pro: innovations in test program generation for functional processor verification , 2004, IEEE Design & Test of Computers.
[33] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[34] B. Aktan,et al. Improving evolutionary algorithm performance on maximizing functional test coverage of ASICs using adaptation of the fitness criteria , 2002, Proceedings of the 2002 Congress on Evolutionary Computation. CEC'02 (Cat. No.02TH8600).
[35] Thorsten Grotker,et al. System Design with SystemC , 2002 .
[36] Santanu Chattopadhyay,et al. Genetic algorithm based test scheduling and test access mechanism design for system-on-chips , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[37] Sofiène Tahar,et al. Towards an efficient assertion based verification of SystemC designs , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).
[38] Sofiène Tahar,et al. Efficient Assertion Based Verification using TLM , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[39] Lawrence. Davis,et al. Handbook Of Genetic Algorithms , 1990 .
[40] Sofiène Tahar,et al. Design for verification of SystemC transaction level models , 2005, Design, Automation and Test in Europe.
[41] Samir Palnitkar. Design Verification with e , 2003 .
[42] Yehuda Naveh,et al. Quality improvement methods for system-level stimuli generation , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[43] Avi Ziv,et al. Defining coverage views to improve functional coverage analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..
[44] Michael Kantrowitz,et al. I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor , 1996, DAC '96.
[45] Pinaki Mazumder,et al. Genetic Algorithms for VLSI Design, Layout and Test Automation , 1998 .
[46] David G. Chinnery,et al. A functional validation technique: biased-random simulation guided by observability-based coverage , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.
[47] Jie Yao,et al. CellNet Co-Ev: Evolving Better Pattern Recognizers Using Competitive Co-evolution , 2004, GECCO.
[48] David E. Goldberg,et al. Genetic Algorithms in Search Optimization and Machine Learning , 1988 .
[49] Giovanni Squillero,et al. Fully automatic test program generation for microprocessor cores , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.