Design of the processing node of the PTAH 64 parallel computer

Abstract This paper presents the design of the Processing Node (PN) for an implementation of the PTAH architectural model with 64 PNs. The PTAH architecture is presented. The requirements of a 64 PNs implementation are derived. The design tradeoff for the global Processing Node architecture, the control system, the Floating Point and Integer Unit and the data memory is discussed. Finaly the instruction formats are presented.

[1]  David T. Harper,et al.  Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems , 1991, IEEE Trans. Parallel Distributed Syst..

[2]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[3]  Jack Dongarra,et al.  Experimental parallel computing architectures , 1987 .

[4]  Franck Cappello,et al.  Data layouts impacts on the compilation of the communications for a synchronous MSIMD machine , 1992, Microprocess. Microprogramming.

[5]  D. Etiemble,et al.  An interconnection network and a routing scheme for a massively parallel message-passing multicomputer , 1990, [1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation.

[6]  Franck Cappello,et al.  PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing , 1992, PARLE.

[7]  Gary M. Johnson.  Exploiting parallelism in computational science , 1989, Future Gener. Comput. Syst..

[8]  Howard Jay Siegel,et al.  PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition , 1981, IEEE Transactions on Computers.

[9]  Allan Gottlieb,et al.  Highly parallel computing , 1989, Benjamin/Cummings Series in computer science and engineering.