Very long instruction work architectures and the ELI-512
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[1] Michael J. Flynn,et al. Detection and Parallel Execution of Independent Instructions , 1970, IEEE Transactions on Computers.
[2] Edward M. Riseman,et al. The Inhibition of Potential Parallelism by Conditional Jumps , 1972, IEEE Transactions on Computers.
[3] Edward M. Riseman,et al. Percolation of Code to Enhance Parallel Dispatching and Execution , 1972, IEEE Transactions on Computers.
[4] Alfred V. Aho,et al. Principles of Compiler Design , 1977 .
[5] Alfred V. Aho,et al. Principles of Compiler Design (Addison-Wesley series in computer science and information processing) , 1977 .
[6] David A. Patterson,et al. Towards an efficient, machine-independent language for microprogramming , 1979, MICRO 12.
[7] Subrata Dasgupta,et al. The Organization of Microprogram Stores , 1979, CSUR.
[8] Joseph A. Fisher,et al. 2n-way jump microinstruction hardware and an effective instruction binding method , 1980, SIGM.
[9] David A. Padua,et al. High-Speed Multiprocessors and Compilation Techniques , 1980, IEEE Transactions on Computers.
[10] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[11] Alexandru Nicolau,et al. Using an oracle to measure potential parallelism in single instruction stream programs , 1981, MICRO 14.
[12] Thomas R. Gross,et al. Optimizing delayed branches , 1982, MICRO 15.
[13] Norman P. Jouppi,et al. MIPS: A microprocessor architecture , 1982, MICRO 15.
[14] Dean Jacobs,et al. Monte Carlo techniques in code optimization , 1982, MICRO 15.
[15] Carlo H. Séquin,et al. A VLSI RISC , 1982, Computer.