A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain

A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

[1]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[2]  M.J. Flynn,et al.  Deep submicron microprocessor design issues , 1999, IEEE Micro.

[3]  Anders Lansner,et al.  Non-commercial Research and Educational Use including without Limitation Use in Instruction at Your Institution, Sending It to Specific Colleagues That You Know, and Providing a Copy to Your Institution's Administrator. All Other Uses, Reproduction and Distribution, including without Limitation Comm , 2022 .

[4]  Karthikeyan Sankaralingam,et al.  Dark silicon and the end of multicore scaling , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[5]  J. Thomas Pawlowski,et al.  Hybrid memory cube (HMC) , 2011, 2011 IEEE Hot Chips 23 Symposium (HCS).

[6]  Kwabena Boahen,et al.  Point-to-point connectivity between neuromorphic chips using address events , 2000 .

[7]  Wei Yang Lu,et al.  Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.

[8]  Ahmed Hemani,et al.  Distributed Runtime Computation of Constraints for Multiple Inner Loops , 2013, 2013 Euromicro Conference on Digital System Design.

[9]  Ahmed Hemani,et al.  Address generation scheme for a coarse grain reconfigurable architecture , 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

[10]  Murray Shanahan,et al.  Accelerated simulation of spiking neural networks using GPUs , 2010, The 2010 International Joint Conference on Neural Networks (IJCNN).

[11]  Johannes Schemmel,et al.  A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems , 2010, Biological Cybernetics.

[12]  Nikil D. Dutt,et al.  An Efficient Simulation Environment for Modeling Large-Scale Cortical Processing , 2011, Front. Neuroinform..

[13]  Myron Flickner,et al.  Compass: A scalable simulator for an architecture for cognitive computing , 2012, 2012 International Conference for High Performance Computing, Networking, Storage and Analysis.

[14]  Anders Lansner,et al.  A Higher order Bayesian Neural Network with Spiking Units , 1996, Int. J. Neural Syst..

[15]  Anders Lansner,et al.  Spiking brain models: Computation, memory and communication constraints for custom hardware implementation , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[16]  Örjan Ekeberg,et al.  Brain-scale simulation of the neocortex on the IBM Blue Gene/L supercomputer , 2008, IBM J. Res. Dev..

[17]  Dharmendra S. Modha,et al.  Cognitive Computing , 2011, Informatik-Spektrum.

[18]  H. Markram.  The Blue Brain Project , 2006, Nature Reviews Neuroscience.

[19]  Jim D. Garside,et al.  SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation , 2013, IEEE Journal of Solid-State Circuits.

[20]  Johannes Schemmel,et al.  Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system , 2012, 2012 IEEE International Symposium on Circuits and Systems.