A novel non-disjunctive method for decomposition of CPLDs

[1]  Martin Bolton Digital systems design with programmable logic , 1990, Electronic systems engineering series.

[2]  Shih-Chieh Chang,et al.  Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Rolf Drechsler,et al.  Advanced BDD optimization , 2005 .

[4]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[5]  S. Minato Binary Decision Diagrams and Applications for VLSI CAD , 1995 .

[6]  Adam Milik,et al.  A novel method of two-stage decomposition dedicated for PAL-based CPLDs , 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

[7]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Jae-Jin Kim,et al.  Development of technology mapping algorithm for CPLD under time constraint , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[10]  TingTing Hwang,et al.  A technology mapping algorithm for CPLD architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[11]  Hi-Seok Kim,et al.  An efficient CPLD technology mapping under the time constraint , 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

[12]  Kenneth Yan Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks , 2001, ASP-DAC '01.

[13]  Massoud Pedram,et al.  FPGA synthesis using function decomposition , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[14]  Massoud Pedram,et al.  OBDD-based function decomposition: algorithms and implementation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  A. El Gamal,et al.  PLA-based FPGA Area Versus Cell C+ Granularity , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[16]  R. Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.

[17]  Jing-Yang Jou,et al.  ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[19]  Jason Helge Anderson,et al.  Technology mapping for large complex PLDs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).