A Hybrid Power Reduction Scheme Using Pipeline Stage Unification and Dynamic Voltage Scaling

Recent mobile processors have been required to provide both low-power consumption and high performance. To satisfy these requirements, we previously proposed pipeline stage unification (PSU), and showed that it can reduce energy consumption more than that of dynamic voltage scaling (DVS). This paper proposes a hybrid control scheme that combines PSU and DVS to enhance PSU. This scheme dynamically changes the number of pipeline stages, clock frequency, and supply voltage according to the required throughput. Our evaluation results in various throughput show that our scheme reduces power consumption by a maximum of 44% compared to DVS.