Sinusoidal Pulse Width Modulation (SPWM) Design and Implementation by Focusing on Reducing Harmonic Content

This paper is focusing on optimizing harmonic content in Sinusoidal Pulse Width Modulation (SPWM) design. This SPWM is designed using VHDL and implemented on ALTERA (DE2-70 board). SPWM output is generated by intersection between sine signal and triangle signal. Sine signal is the reference waveform and triangle waveform is the carrier waveform. When value sine signal is large than triangle signal, the pulse will start produce to high. And then when the triangular signals higher than sine signal, the pulse will come to low. SPWM output will changed by changing the value of number of bit, modulation index and frequency used in this system to produce more pulse width. The more pulse width produced, the output voltage will have lower harmonics contents and the resolution increase.

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