Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories

This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.

[1]  Willy Sansen,et al.  analog design essentials , 2011 .

[2]  A. Boni,et al.  LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS , 2001 .

[4]  Koh Chin Yeong,et al.  1.2Gbps LVDS interface , 2007, 2007 International Symposium on Integrated Circuits.

[5]  J. Silva-Martinez,et al.  Low-voltage low-power LVDS drivers , 2005, IEEE Journal of Solid-State Circuits.

[7]  Alberto Stabile.  FTK: A hardware real-time track finder for the ATLAS trigger system , 2016, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST).