Design and migration challenges for an Alpha microprocessor in a 0.18 /spl mu/m copper process

An Alpha microprocessor design is implemented in a 0.18 /spl mu/m CMOS process, utilizing 7 layers of copper interconnect. Process features include nominal and low Vt transistor options, low-K FSG dielectric and a refractory metal local interconnect layer. The design is leveraged from a 0.35 /spl mu/m aluminum design. It contains 15.5M transistors on a 10/spl times/12 mm/sup 2/ die and is packaged in a flip chip ceramic land grid array. The microprocessor runs with a 1.65 V nominal supply and consumes 65 W. This microprocessor operates at >1.3 GHz.