Source-degenerated CMOS Transconductor with Auxiliary Linearization

We propose a linearization technique, for CMOS differential pairs employing resistive source degeneration, which exploits the bulks of the pair as additional control terminals. Simulations were performed using a 0.25-mum process, on an example design powered with 2.5 V and 1 mA. Compared to the traditional source-degenerated transconductor, the proposed approach allows a THD reduction in the voltage-to-current conversion by 10 dB, for an input differential signal of 0.5 Vpp and for frequencies up to 100 MHz.

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