A technique for nonlinearity self-calibration of DLLs
暂无分享,去创建一个
[1] H.-J. Jentschel,et al. An analogue delay line for virtual clock enhancement in DDS , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[2] J. Doernberg,et al. Full-speed testing of A/D converters , 1984 .
[3] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .
[4] H.-J. Jentschel,et al. A virtual clock enhancement method for DDS using an analog delay line , 2001 .
[5] Pietro Andreani,et al. A Digitally Controlled Shunt Capacitor CMOS Delay Line , 1999 .
[6] Timo Rahkonen,et al. A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[7] M. Mota,et al. A high-resolution time interpolator based on a delay locked loop and an RC delay line , 1999, IEEE J. Solid State Circuits.
[8] Pietro Andreani,et al. Multihit multichannel time-to-digital converter with /spl plusmn/1% differential nonlinearity and near optimal time resolution , 1998 .
[9] P. R. Gray,et al. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000 .
[10] Luca Fanucci,et al. On the differential nonlinearity of time-to-digital converters based on delay-locked-loop delay lines , 2001 .
[11] Luca Fanucci,et al. On-line calibration for non-linearity reduction of delay-locked delay-lines , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).