SoC BUS : The solution of high communication bandwidth on chip and short TTM

The paper is divided into two parts. The first part of the paper gives the motivation to use SoC bus for system integration of a SoC as well as a brief review of the SoC concept, IP reuse, and research on SoC bus and SoC interconnect network. We define the SoC network as “classical SoC network” that delivers data packets on a network. We point out in the paper that the classical SoC network introduces long data latency and contributes to high silicon cost. In the second part of the paper, we introduce the SoC bus research from Linkoping University. We introduce a novel concept, PCC: Packet Connected Circuit. Based on PCC, a data transaction is initialized by packet routing. The rout is locked as a bus circuit after proving and acknowledging the rout. Therefore, we reach fixed and low transfer latency based on high bandwidth supporting multiple simultaneous data transfer. At the same time, buffers in the nodes are eliminated so that the silicon cost of a SoC network becomes feasible. MESA and MISA models are proposed for improving wrappers. A SoC system designer’s methodology is proposed so that a short TTM (Time To Market) SoC design is possible.