Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

We have proposed a single metal/dual high-k gate stack for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-k dielectrics, such as MgO- and Al2O3-containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.

[1]  D. Campbell,et al.  Selection of thin film capacitor dielectrics , 1968 .

[2]  A. Toriumi,et al.  Reliable Extractions of EOT and Vfb in Poly-Si Gate High-k MISFETs through Advanced Modeling of Gate and Substrate Capacitances , 2005 .

[3]  T. Nabatame,et al.  Re-examination of Flat-Band Voltage Shift for High-k MOS Devices , 2007, 2007 IEEE Symposium on VLSI Technology.

[4]  D. Gilmer,et al.  Application of group electronegativity concepts to the effective work functions of metal gate electrodes on high- κ gate oxides , 2007 .

[5]  B.H. Lee,et al.  Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[6]  R. Choi,et al.  Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[7]  J. Robertson Band offsets of wide-band-gap oxides and implications for future electronic devices , 2000 .

[8]  C.H. Diaz,et al.  An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.

[9]  A. Toriumi,et al.  Comprehensive Study of VFB Shift in High-k CMOS - Dipole Formation, Fermi-level Pinning and Oxygen Vacancy Effect , 2007, 2007 IEEE International Electron Devices Meeting.

[10]  Ming-Fu Li,et al.  Dual Metal Gates with Band-Edge Work Functions on Novel HfLaO High-K Gate Dielectric , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[11]  J.C.S. Woo,et al.  TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling , 2004, IEEE Transactions on Semiconductor Manufacturing.

[12]  M. Ieong,et al.  Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[13]  Extendibility of High Mobility HfSiON Gate Dielectrics , 2005 .

[14]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[15]  D. Schlom,et al.  Thermodynamic stability of binary oxides in contact With silicon , 1996 .

[16]  Tsuneo Terasawa,et al.  Three-dimensional metrology with side-wall measurement using tilt-scanning operation in digital probing AFM , 2006, SPIE Advanced Lithography.

[17]  A. Toriumi,et al.  Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlO/sub x/(N) CMOSFETs , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..