Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology

This paper enumerates low power, high speed design of SET, DET, TSPC and C2CMOS Flip-Flop. As these flip flop topologies have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flops are analyzed at 90nm technologies. The above designed Flip-Flops and Latches are compared in terms of its area, transistor count, power dissipation and propagation delay using DSCH and Microwind tools. As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance is implemented in layout level which develops the low power consumption chip using recent CMOS micron layout tools. This project proposes low power high speed design of flip flops in which True Single Phase Clocking (TSPC) and C2CMOS flip flop compared with existing flip flop topologies in term of its area, transistor count, power dissipation, propagation delay, parasitic values with the simulation results in microwind.