Enhancement of tolerances in transmission systems by analog and digital processing

On the following pages we address some actual topics of analog and digital electronic equalisation for 10 and 40 Gbit/s transmission. Analog circuits currently overcome the bandwidth limits for 40Gb/s operation. With first 5 tap feed forward equaliser (FFE) SiGe chips CD and PMD tolerance enhancement can be demonstrated. According to numerical simulations, the combination of the FFE with a one-stage decision feedback equaliser (DFE) should be a good choice to mitigate signal degradation caused by various effects. At 10 Gb/s more complex signal processing based on digitalsignal-processing (DSP) is already implemented in first products as maximum likelihood sequence estimator (MLSE, also referred to as Viterbi equaliser VE) or in a lab prototype of soft error correction (soft FEC). Detailed numerical studies on the performance of the VE reveal that opposite to the analog FFE+DFE, low electrical bandwidth cannot be handled by the standard MLSE scheme and an extension of the processing algorithm is needed. Though the combination of an MLSE based equaliser and soft-FEC has the potential to lead to further improvement, numerical analysis of turbo equalisers combining distortion mitigation and error correction in an iterative way indicate that with a FEC overhead in the range of 7% only moderate equalisation improvement seems to be possible.

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