Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation

Nanoscale VLSI systems are subject to increasingly significant performance variability. Accurate timing analysis and effective silicon-based performance verification techniques are critical to successful nanoscale VLSI design. The state-of-the-art statistical static timing analysis (SSTA) techniques cannot capture performance variability due to primary inputs and sequential element states which, however, is critical to path delay test generation. In this paper, we present the first dynamic statistical timing analysis-based VLSI path delay test pattern generation technique. We observe that VLSI timing analysis and power estimation target the same signal toggling activity. By leveraging the existing power estimation techniques, we have developed signal-probability-based statistical timing analysis (SPSTA), and SPSTA-based VLSI delay test pattern generation (SPSTA-DTPG) techniques. Our experimental results based on ISCAS'89 benchmark circuits show that the state-of-the-art statistical static timing analysis-based delay test pattern generation (SSTA-DTPG) achieves an average of 47.32%, 45.14%, and 57.98%, SPSTA-DTPG achieves an average of 57.41%, 61.43%, and 68.05%, while signal probability-based statistical timing analysis-based delay test pattern generation with (test pattern) compaction (SPSTA-DTPG-C) achieves an average of 83.09%, 87.48% and 90.30% coverage of the top 50, 100, and 200 timing-critical paths, respectively.

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