A motion video compression LSI with distributed arithmetic architecture

The authors summarize the algorithm, architecture, and implementation of an LSI that can perform discrete cosine transform (DCT), inverse DCT (IDCT), motion estimation (ME), and video data statistical processing for inter/intra decision (DECISION) at 2.59 GOPS (giga operations per second). This LSI can perform the DCT, IDCT, ME and DECISION in a single chip by switching mode signals. The LSI has a power consumption of 2 W at 40.5-MHz input clock. The chip, designed in a 0.8-/spl mu/m, double-metal CMOS technology, has 405,000 transistors and a die size of 13.86 /spl times/ 13.51 mm/sup 2/.