A 256K CMOS SRAM with variable-impedance loads

A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.

[1]  T. Masuhara,et al.  A 20ns 64K CMOS SRAM , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  K.C. Hardee,et al.  A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM , 1981, IEEE Journal of Solid-State Circuits.

[3]  S. Kohyama,et al.  A 64Kb CMOS RAM , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  T. Yasui,et al.  Hi-CMOS III technology , 1984, 1984 International Electron Devices Meeting.