A High-level Interconnect Power Model for Design Space Exploration

In this paper, we present a high-level power model toestimate the power consumption in semi-global and global interconnects.Such interconnects are used for communications between logic modules,clock distribution networks, and power supply rails. The main purposeof our model is to set forward a simple methodology to efficiently obtainfirst-order estimates of interconnect power in early stages of the designprocess. Hence, the objective is to provide designers and/or high-leveldesign automation tools with a way to quickly explore the design spaceand weed out architectures whose interconnect power requirements donot meet the allocated power budget. In addition to switching power,which includes inter-wire coupling, our model also considers power dueto vias and repeaters. Our experimental results show that in comparisonto an accurate low-level model, the error in our method in estimatingtotal switching power is only 6% (while the speedup is three-to-fourorders of magnitude), and an estimate of the numbers of vias (hence, viapower) is within 3% agreement of that obtained for designs synthesizedby commercial tools. Furthermore, we develop a probabilistic segmentlength distribution model for cases in which Rent's rule is inadequate. Byanalyzing the netlists of a set of complex designs, we have been able tovalidate our segment length distribution model. The novelty of this worklies in the introduction of a high-level interconnect modeling methodologyin which it is possible to efficiently compute all the major sources ofpower consumption in interconnects and hence, enable interconnect-aware,high-level design space exploration.

[1]  Jason Cong,et al.  An interconnect-centric design flow for nanometer technologies , 2001, Proc. IEEE.

[2]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[3]  Massoud Pedram,et al.  Interconnect energy dissipation in high-speed ULSI circuits , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Dennis Sylvester,et al.  Analytical modeling and characterization of deep-submicrometer interconnect , 2001 .

[5]  Jason Cong,et al.  Interconnect performance estimation models for design planning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[7]  Niraj K. Jha,et al.  Interconnect-aware high-level synthesis for low power , 2002, ICCAD 2002.

[8]  Sujit Dey,et al.  Modeling and minimization of interconnect energy dissipation in nanometer technologies , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Thomas N. Theis,et al.  The future of interconnection technology , 2000, IBM J. Res. Dev..

[10]  Sachin S. Sapatnekar,et al.  Exact and efficient crosstalk estimation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[12]  Jason Cong,et al.  An interconnect energy model considering coupling effects , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[13]  Sujit Dey,et al.  Register transfer level power optimization with emphasis on glitch analysis and reduction , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Prithviraj Banerjee,et al.  Simultaneous scheduling, binding and floorplanning in high-level synthesis , 1998, Proceedings Eleventh International Conference on VLSI Design.

[15]  Dirk Stroobandt,et al.  Recent Advances in System-Level Interconnect Prediction. , 2000 .

[16]  Pawan Kapur,et al.  Power estimation in global interconnects and its reduction using a novel repeater optimization methodology , 2002, DAC '02.

[17]  Niraj K. Jha,et al.  SCALP: an iterative-improvement-based low-power data path synthesis system , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Anantha Chandrakasan,et al.  A bus energy model for deep submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[19]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[20]  Niraj K. Jha,et al.  MOCSYN: multiobjective core-based single-chip system synthesis , 1999, DATE '99.

[21]  Jan M. Rabaey,et al.  Low-power architectural synthesis and the impact of exploiting locality , 1996, J. VLSI Signal Process..

[22]  J. A. Connelly.  Integrated Circuits , .

[23]  Kurt Keutzer,et al.  System-Level Performance Modeling with BACPAC - Berkeley Advanced Chip Performance Calculator , 1999 .

[24]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[25]  Dennis Sylvester,et al.  An Analytical Crosstalk Model with Application to ULSI Interconnect Scaling , 1998 .

[26]  Taewhan Kim,et al.  Bus optimization for low-power data path synthesis based on network flow method , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).