An adaptive FPGA and its distributed routing

Every commercially available FPGA supplies high routing capabilities. However, placement and routing are processed by a computer before being sent to the chip. This nonadaptive feature does not fit well with bio-inspired applications such as growing systems or neural networks with changing topology. Therefore we propose a new kind of routing, built in hardware and totally distributed. Unlike previous works about routing, our approach does not need a central control over the process. In this paper we present a new FPGA embedding this algorithm, as well as the basic idea of our architecture, based on a parallel implementation of Lee shortest path algorithm. We then present a second algorithm that decreases the number of possible congestions, a third that reduces the execution time, and a fourth that combines both techniques. Finally we introduce different neighborhoods and compare all these algorithms in terms of area, speed, path length and congestion.