论文信息 - Logarithmic Number System and Floating-Point Arithmetics on FPGA

Logarithmic Number System and Floating-Point Arithmetics on FPGA

An introduction to a logarithmic number system (LNS) is presented. Range and precision of this arithmetic is briefly discussed. We show that the LNS arithmetic is suitable for a FPGA implementation. A case study will compare parameters of our LNS arithmetic library to a conventional floating-point arithmetic.

[1] Mark G. Arnold,et al. Applying Features of IEEE 754 to Sign/Logarithm Arithmetic , 1992, IEEE Trans. Computers.

[2] John N. Coleman,et al. A 32 bit logarithmic arithmetic unit and its performance compared to floating-point , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[3] David Lewis,et al. A 30-b integrated logarithmic number system processor , 1991 .

[4] J. N. Coleman. Simplification of table structure in logarithmic arithmetic , 1995 .

[5] Earl E. Swartzlander,et al. The Sign/Logarithm Number System , 1975, IEEE Transactions on Computers.

[6] Jirí Kadlec,et al. Arithmetic on the European Logarithmic Microprocessor , 2000, IEEE Trans. Computers.