Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

[1]  Jingshi Yao,et al.  Power Amplifier Selection for LINC Applications , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Michiel Steyaert,et al.  A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[3]  Yorgos Palaskas,et al.  A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement , 2012, IEEE Journal of Solid-State Circuits.

[4]  An-Yeu Wu,et al.  Multilevel LINC System Designs for Power Efficiency Enhancement of Transmitters , 2009, IEEE Journal of Selected Topics in Signal Processing.

[5]  H. Chireix High Power Outphasing Modulation , 1935, Proceedings of the Institute of Radio Engineers.

[6]  David R. Cox,et al.  Linear Amplification with Nonlinear Components , 1974, IEEE Trans. Commun..

[7]  Ted Johansson,et al.  A Review of Watt-Level CMOS RF Power Amplifiers , 2014, IEEE Transactions on Microwave Theory and Techniques.