Testing of glue logic interconnects using boundary scan architecture

The authors propose test schemes for glue logic (non-boundary-scan components) interconnects. Testing these interconnects is difficult owing to reduced accessibility and glue-logic function-dependent outputs. The proposed schemes address these testability issues and provide efficient boundary-scan based techniques. The tests are applied under the B-Scan DFT (design-for-testability) environment as scan tests. Thus, issues such as ease of test vector generation, test vector loading time, and test application time are very important for the proposed schemes. The application of the test schemes is described.<<ETX>>

[1]  John Bateson.  In-Circuit Testing , 1985 .

[2]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[3]  T. Muto.  Some reliability problems of surface-mounted devices , 1988, IEEE Circuits and Devices Magazine.

[4]  R. G. Bennetts.  Introduction to Digital Board Testing , 1982 .

[5]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[6]  F.P.M. Beenker,et al.  Macro Testing: Unifying IC And Board Test , 1986, IEEE Design & Test of Computers.

[7]  Paul Wagner,et al.  INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .

[8]  J. Turino.  IEEE P1149 Proposed Standard Testability Bus-An update with case histories , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[9]  Matthias Gruetzner.  Design for testability for wafer-scale integration interconnect systems design and test methodology , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[10]  Prabhakar Goel,et al.  Electronic Chip-In-Place Test , 1982, 19th Design Automation Conference.

[11]  L. Whetsel.  A proposed standard test bus and boundary scan architecture , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.