Finite element modeling on electromigration of TSV interconnect in 3D package

Through silicon vias (TSV) are very important components in 3D integrated circuits, because they are responsible for the vertical connection inside the package. In this paper, a finite element model on electromigration is established to investigate the mass diffusion phenomenon for TSV interconnect in 3D stacked structure. Electric-thermo-mechanical coupled analysis is carried out to obtain the current density, temperature and stress distribution of TSV structure under high current density load. Atomic flux divergence is calculated By ANSYS APDL to evaluate electromigration failure of TSV structure. The different migration effects in the electromigration modeling of the TSV structure is also discussed.

[1]  Yong Liu,et al.  3D Modeling of Electromigration Combined with Thermal-Mechanical Effect for IC Device and Package , 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

[2]  X. Fan,et al.  Finite element modeling on electromigration of solder joints in wafer level packages , 2010, Microelectron. Reliab..

[3]  Cher Ming Tan,et al.  Electromigration performance of Through Silicon Via (TSV) - A modeling approach , 2010, Microelectron. Reliab..

[4]  John H. Lau,et al.  Evolution and outlook of TSV and 3D IC/Si integration , 2010, 2010 12th Electronics Packaging Technology Conference.

[5]  Jiwoo Pak,et al.  Modeling of electromigration in through-silicon-via based 3D IC , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[6]  Yasumitsu Orii,et al.  Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package , 2012 .

[7]  Xin Zhao,et al.  Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Electromigration reliability of open TSV structures , 2014 .

[9]  H. Ceric,et al.  Analysis of electromigration void nucleation failure time in open copper TSVs , 2015, 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[10]  Effect of Design Parameters on Thermomechanical Stress in Silicon of Through-Silicon Via , 2016 .

[11]  Austin Lancaster,et al.  Integrated circuit packaging review with an emphasis on 3D packaging , 2018, Integr..