Power Modeling and Characterization

Previous related works in power computation at different levels of design models are demonstrated in this chapter. It exposes the flow of previous methodologies in details including their pros and cons according to feasibility and cost of implementation. Also, potential contributions of the proposed TLPM methodology are presented.

[1]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[2]  Jean-Luc Dekeyser,et al.  Estimating Energy Consumption for an MPSoC Architectural Exploration , 2006, ARCS.

[3]  Florence Maraninchi,et al.  System-level modeling of energy in TLM for early validation of power and thermal management , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Dam Sunwoo,et al.  PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[5]  Rajesh Gupta,et al.  Evaluating the effectiveness of model-based power characterization , 2011 .

[6]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[7]  Luciano Lavagno,et al.  Efficient power co-estimation techniques for system-on-chip design , 2000, DATE '00.

[8]  Wolfgang Porod,et al.  Single-electron transistor analyticI–Vmodel for SPICE simulations , 2000 .

[9]  Luca Benini,et al.  System-level power estimation and optimization , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[10]  Luca Benini,et al.  Cycle-accurate simulation of energy consumption in embedded systems , 1999, DAC '99.

[11]  Narayanan Vijaykrishnan,et al.  A power estimation methodology for systemC transaction level models , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[12]  Nuria Pazos,et al.  System level performance estimation of multi-processing, multi-threading SoC architectures for networking applications , 2003 .

[13]  Miodrag Potkonjak,et al.  Function-level power estimation methodology for microprocessors , 2000, DAC.

[14]  Srivaths Ravi,et al.  Hardware accelerated power estimation , 2005, Design, Automation and Test in Europe.

[15]  Farid N. Najm,et al.  Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Vijay Degalahal,et al.  Methodology for high level estimation of FPGA power consumption , 2005, ASP-DAC '05.

[17]  Yunjian Jiang,et al.  State-based power analysis for systems-on-chip , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  Luciano Lavagno,et al.  Cosimulation-based power estimation for system-on-chip design , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Anand Raghunathan,et al.  Power monitors: a framework for system-level power estimation using heterogeneous power models , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[20]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[21]  Niraj K. Jha,et al.  Register-transfer level estimation techniques for switching activity and power consumption , 1996, ICCAD 1996.

[22]  Jean-Luc Dekeyser,et al.  An MPSoC Performance Estimation Framework Using Transaction Level Modeling , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[23]  Srivaths Ravi,et al.  Power estimation for cycle-accurate functional descriptions of hardware , 2004, ICCAD 2004.

[24]  Frank Vahid,et al.  A hybrid approach for core-based system-level power modeling , 2000, ASP-DAC '00.

[25]  Subhrajit Bhattacharya,et al.  SEAS: a system for early analysis of SoCs , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[26]  Sherief Reda.  Thermal and Power Characterization of Real Computing Devices , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[27]  Alberto L. Sangiovanni-Vincentelli,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Vittorio Zaccaria,et al.  System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip , 2004, Ultra Low-Power Electronics and Design.

[29]  Jörg Henkel,et al.  Instruction-based system-level power evaluation of system-on-a-chip peripheral cores , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[30]  Stephen Dean Brown.  FPGA Architectural Research: A Survey , 1996, IEEE Des. Test Comput..

[31]  Adam Donlin,et al.  Transaction level modeling: flows and use models , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[32]  Peng Yang,et al.  PowerViP: SoC power estimation framework at transaction level , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[33]  Farid N. Najm,et al.  Power modeling for high-level power estimation , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[34]  Laurent Maillet-Contoz,et al.  Using transactional level models in a SoC design flow , 2003 .

[35]  Pascal Vivet,et al.  Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[36]  Jörg Henkel,et al.  A framework for estimation and minimizing energy dissipation of embedded HW/SW systems , 1998, DAC.

[37]  L. Benini,et al.  Lookup table power macro-models for behavioral library components , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[38]  Mary Jane Irwin,et al.  Architecture-level power estimation and design experiments , 2001, TODE.

[39]  Farid N. Najm,et al.  Towards a high-level power estimation capability [digital ICs] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[40]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[41]  Sherief Reda,et al.  Power Modeling and Characterization of Computing Devices: A Survey , 2012, Found. Trends Electron. Des. Autom..

[42]  Ravi Shankar,et al.  A comparative study of modelling at different levels of abstraction in system on chip designs: a case study , 2004, IEEE Computer Society Annual Symposium on VLSI.

[43]  Bruce Jacob,et al.  Accurate and fast system-level power modeling: An XScale-based case study , 2007, TECS.

[44]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[45]  David J. Greaves,et al.  TLM POWER3: Power estimation methodology for SystemC TLM 2.0 , 2012, Proceeding of the 2012 Forum on Specification and Design Languages.

[46]  Massimo Conti,et al.  Power estimation in embedded systems within a SystemC-based design context: The PKtool environment , 2009, 2009 Seventh Workshop on Intelligent solutions in Embedded Systems.

[47]  R. Ben Atitallah,et al.  MPSoC power estimation framework at transaction level modeling , 2007, 2007 Internatonal Conference on Microelectronics.