A power modelling and characterization method for logic simulation

This paper presents a method for accurate characterization of power dissipation by logic elements in integrated circuits that accounts for input slew rate, output capacitive loading, capacitive feedthrough effects, and logic state dependencies. A practical method to characterize power is described. Compared to current implementations, this characterization method drastically reduces the number of circuit simulations required for cell library characterizations. It makes feasible power analysis at logical simulation speeds with Spice-like accuracy. Errors of the model predictions are within 8% of Spice results.

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