Extraction of functional regularity in datapath circuits

Datapath circuits exhibit a very high degree of regularity, which is exploited by designers to generate layouts with a high density and performance as well as to reduce the overall design effort. Regularity in a datapath circuit manifests itself at functional, structural, and topological levels. Functional regularity of a circuit implies the existence of logically equivalent subcircuits-a common feature of datapath circuits. We present a new and comprehensive approach to extract functional regularity for datapath circuits from their high-level or gate-level descriptions. The key step is the generation of a large set of templates, where a template is a subcircuit with multiple instances in the circuit. Two novel template generation algorithms are presented-one for templates with a tree structure, and the other for a special class of multioutput templates, called single-principal-output-graph (SPOG) templates, where all outputs of a template are in the transitive fanin of a particular output. The set of templates generated is shown to be complete under a few simplifying, yet practical, assumptions, which is key in obtaining a desirable cover of the circuit using templates. We present a few extensions to our regularity extraction approach to demonstrate its generality; these extensions include hierarchical representation of regularity and generation of instances of user-specified templates. We show that the generation of the above two classes of templates results in good covers for datapath circuits with a regular bus structure, including several International Conference on Computer-Aided Design benchmark circuits. The regularity extracted from these circuits can be used to easily understand their structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general-purpose microprocessors.

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