Effective datapath logic extraction techniques using connection vectors

Datapath macros are essential components of integrated circuits. The high regularity of datapaths allows compact layout design during placement. In some cases, datapath macros are manually pre-designed and pre-placed. However, datapath macros are frequently mixed with other circuits and they need to be extracted to capitalise on their regularity. In this study, the cells of a given circuit are accurately classified based on their size and pin information, and novel connection vectors to represent aspects of the connectivity among the cells have been proposed. By using the connection vectors of the cells, the similarity of connections is evaluated to extract potential datapath stages that constitute functional steps of a datapath. Two new efficient datapath logic extraction techniques (EDLETs) have been implemented based on the connection vectors for extracting potential datapaths in the circuit. One is the procedure-based method, and the other is the machine learning-based method. When compared with state-of-the-art methods, the experiments show that both the procedure-based and the learning-based methods proposed in this study efficiently extract potential datapaths from the Modified International Symposium on Physical Design (MISPD) 2011 Datapath Benchmark Suite. The extraction results of the proposed EDLET can be forwarded to a datapath placement tool for placing datapaths with a regular structure.

[1]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yu Wang,et al.  Effective regularity extraction and placement techniques for datapath-intensive circuits , 2017, IET Circuits Devices Syst..

[3]  Earl E. Swartzlander,et al.  Structure-Aware Placement Techniques for Designs With Datapaths , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  J. Andres Torres,et al.  High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Gotaro Odawara,et al.  Partitioning and Placement Technique for CMOS Gate Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Yoshua Bengio,et al.  Gradient-based learning applied to document recognition , 1998, Proc. IEEE.

[7]  Iris Hui-Ru Jiang,et al.  Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction , 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Dongjin Lee,et al.  SimPL: An effective placement algorithm , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).