An Instruction Throughput Model of Superscalar Processors

Advances in semiconductor technology enable larger processor design spaces, leading to increasingly complex systems. At an initial stage, designers must evaluate many architecture design points to achieve a suitable design. Currently, most architecture exploration is performed using cycle accurate simulators. Although accurate, these tools are slow, thus limiting a comprehensive design search. The vast design space of today's complex processors and time to market economic pressures motivate the need for faster architectural evaluation methods. This paper presents a superscalar processor performance model that enables rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by quickly identifying promising areas for more thorough and time consuming exploration with traditional tools. The model estimates the instruction throughput of a superscalar processor based on early architectural design parameters and application properties. It has been validated with the SimpleScalar out-of-order simulator. The core of the model, which executes 1.6 million times faster, produces instruction throughput estimates that are with within 5.5 percent of the corresponding SimpleScalar values.

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